1. Field of the Invention
The present invention relates to In-System Programming of programmable integrated circuits. In particular, the present invention relates to reprogramming a programmable integrated circuit in its operational environment without requiring reset of the system in which the programmable integrated circuit is a part.
2. Discussion of the Related Art
In-system programming (ISP) refers to a technique by which a programmable logic device (PLD), e.g., a complex PLD (CPLD) or a field programmable gate array (FPGA) can be reprogrammed or reconfigured without being taken out of its operational environment, such as a printed circuit board. In-System programming techniques are disclosed, for example, in U.S. Pat. No. 5,237,218, entitled "Structure and Method for Multiplexing Pins for In-System Programming" to Josephson et al, and in U.S. Pat. No. 5,635,855, entitled "Method for Simultaneous Programming of In-System Programmable Integrated Circuits," to Tang et al.
Typically, upon entering ISP mode, e.g., by asserting an ISP signal, programming data and commands are shifted serially into an in-system programmable integrated circuit via a serial input pin synchronized by a programming clock signal. During programming, the input and output pins of the ISP integrated circuit are put into a "high impedance" state. Consequently, output signals driven by the integrated circuit to be received into other circuits in the system become indeterminate. Thus, even though ISP can be performed without removal from the system, the system is required to be reset during and after programming to ensure proper operations. In certain applications, such reset operations interrupt service and can be difficult to carried out without manual intervention (e.g., system deployed in satellites), or can be time consuming. Thus, an ability to perform ISP without requiring a reset of the system is desired.
Many ISP integrated circuits also provide support for the IEEE 1149.1 test standard (popularly known as the "boundary scan" or "JTAG" test standard). Under the boundary scan standard, a boundary scan register is provided for each input or output pin of the integrated circuit. Each boundary scan register stores a logic value which can be driven out of the integrated circuit as an output signal of its associated output pin, or driven internally as an input signal from an input pin. One example of an implementation of the boundary scan standard in a PLD is disclosed in U.S. Pat. No. 5,412,260, entitled "Multiplexed Control Pins for In-System Programming and Boundary Scan State Machines in a High Density Programmable Logic Device" to Tsui et al.